1. Technical Field
Embodiments of the present disclosure generally relate to a semiconductor system, and more particularly to semiconductor system for correcting data errors.
2. Related Art
Semiconductor devices may be designed and fabricated to include a test mode function for evaluating the operation thereof. That is, various parameters of the semiconductor devices may be measured in a test mode at a wafer level or at a package level and the tested semiconductor devices may be sorted into passing chips or failed chips according to the test results.
Each of the semiconductor devices may execute a write operation and a read operation to receive and output a plurality of data through pads, and each semiconductor device may be evaluated by sensing logic levels of the data outputted from the pads.
As the semiconductor devices become more highly integrated with the development of fabrication process techniques, the number of failed memory cells in the tested semiconductor devices has been increased. Increase of the number of failed memory cells in the tested semiconductor devices may lead to not only reduction of production yield of the semiconductor devices but also difficulty in the guarantee of a large memory capacity of the semiconductor devices. Accordingly, error correction code (ECC) circuits have been widely employed in the semiconductor devices to solve data errors which are due to the failed memory cells.